Semiconductor devices are used in a variety of electronic applications, such as computers, cellular phones, personal computing devices, and many other applications. Home, industrial, and automotive devices that in the past comprised only mechanical components now have electronic parts that require semiconductor devices, for example. Semiconductor devices are manufactured by depositing many different types of material layers over a semiconductor workpiece or wafer, and patterning the various material layers using lithography. There may be a plurality of transistors, memory devices, switches, conductive lines, diodes, capacitors, logic circuits, and other electronic components formed on a single die or chip.
Capacitors are elements that are used extensively in semiconductor devices for storing an electrical charge. Capacitors essentially comprise two conductive plates separated by an insulator. The capacitance, or amount of charge held by the capacitor per applied voltage, depends on a number of parameters such as the area of the plates, the distance between the plates, and the dielectric constant value of the insulator between the plates, as examples. Capacitors are used in filters, analog-to-digital converters, memory devices, control applications, and many other types of semiconductor devices.
The material layers of semiconductor devices typically comprise thin films of conductive, semiconductive, and insulating materials that are patterned and etched to form integrated circuits (IC's). Each material layer is patterned with a desired pattern, e.g., using a photoresist and/or hard mask as a mask while exposed portions of the material layer are etched away, using dry or wet etch processes, as examples.
The manufacturing of semiconductor devices is typically classified into two phases, the front end of line (FEOL) and the back end of line (BEOL). The BEOL is typically considered to be the point of the manufacturing process where metallization layers are formed, and the FEOL is considered to include the manufacturing processes prior to the formation of metallization layers.
Metallization layers are usually the top-most layers of semiconductor devices. While some integrated circuits have a single top layer of metallization, other integrated circuits comprise multi-level interconnects, as shown in FIG. 1, wherein two or more metallization layers M1, V1, M2, V2, and M3 are formed over a workpiece 102. The metallization layers M1, V1, M2, V2, and M3 include conductive line layers M1, M2, and M3, and via layers V1 and V2. While only five metallization layers M1, V1, M2, V2, and M3 are shown in FIG. 1, in some integrated circuit designs, there may be 8, 10, or even 12 or more conductive line layers M1, M2, M3, . . . Mx separated by via layers V1, V2, . . . Vy, for example.
Each conductive line layer M1, M2, and M3 typically comprises a plurality of conductive lines 106a, 106b, 106c separated from one another by an insulating material 104a, 104c, 104d, also referred to as an inter-level dielectric (ILD). The conductive lines 106a, 106b, and 106c in adjacent horizontal metallization layers M1, M2, and M3 may be connected vertically in predetermined places by vias 108a and 108b formed between the conductive lines 106a, 106b, and 106c, as shown.
The bottom conductive line layer M1 comprising conductive lines 106a makes electrical contact to components formed in and/or on the workpiece 102 in active areas of the semiconductor device 100 in region 112. The top conductive line layer M3 (or layer Mx, not shown in FIG. 1, if there are additional metallization layers, for example) may be used to make electrical connection to another die or to leads of a package, for example, and thus, the top layer of conductive lines, e.g., conductive lines 106c in conductive line layer M3, are typically larger than conductive lines 106a and 106b in the lower conductive line layers M1 and M2, as shown.
Metallization layers M1, V1, M2, V2, and M3 may be formed using subtractive etch processes or by damascene etch processes. In a subtractive etch process, a conductive material is deposited over a wafer, and the conductive material is patterned into the desired conductive feature pattern, such as conductive lines 106a, 106b, and 106c or vias 108a and 108b. A dielectric material is then deposited between the conductive features. In a damascene process, a dielectric material is deposited over a wafer, and then the dielectric material is patterned with a conductive feature pattern. The conductive feature pattern typically comprises a plurality of trenches, for example. The trenches are then filled in with conductive material, and a chemical-mechanical polish (CMP) process is used to remove the excess conductive material from the top surface of the dielectric material. The conductive material remaining within the dielectric material comprises conductive features such as conductive lines 106a, 106b, and 106c and/or vias 108a and 108b.
Damascene processes are typically either single or dual damascene. In a single damascene process, one metallization layer, e.g., M1, V1, or M2 is formed at a time. For example, referring to conductive line layer M1 of FIG. 1, the insulating layer 104a is patterned and then filled with metal, and a CMP process is used to form a single metal layer comprised of conductive lines 106a. In a dual damascene process, two adjacent horizontal insulating layers are patterned, e.g., by forming two lithography patterns in two insulating layers such as layers 104b and 104c, or in a single insulating layer such as layer 104d. The two patterns are then filled with metal, and a CMP process is used to remove excess conductive material from over the insulating layer 104c or 104d, leaving patterned conductive material in the insulating layers. For example, the patterns may comprise conductive lines 106c in one insulating layer portion and vias 108b in the underlying insulating layer portion. Thus, in a dual damascene process, conductor and via trenches are filled in one fill step.
In the past, aluminum was used as a conductive line material in integrated circuits, which is easy to subtractively etch. However, as semiconductor devices are scaled down in size, there is a trend towards the use of copper for interconnect material, which is difficult to subtractively etch, and thus, damascene processes are typically used to form copper conductive features.
CMP processes are used in damascene processes and are also used for global planarization of a semiconductor wafer to remove excess material from over certain topographical features, e.g., after an etch process, for example. It is important for etch processes and CMP processes to have a uniform effect on semiconductor devices during the fabrication process in some designs, so that the various devices formed thereon have uniform electrical parameters. A planar top surface of a semiconductor device at various stages of manufacturing is also important to achieve depth of focus (DOF) for lithography processes, for example.
To ensure planarity of features across the surface of a wafer, “dummy” or non-functional conductive lines and vias are often formed in regions 114 where conductive features, e.g., conductive lines 106a, 106b, and 106c and vias 108a and 108b are not electrically required for the integrated circuit design, e.g., as shown in FIG. 1 in region 114. For example, dummy conductive lines and vias may be formed between areas of widely-spaced conductive lines and vias, to improve planarity. The dummy conductive structures 106a, 106b, 106c, 108a, and 108b are also referred to in the art as “fill structures,” for example.
While dummy conductive lines 106a, 106b, and 106c and vias 108a and 108b in region 114 improve planarity of the material layers of semiconductor devices, they are an inefficient use of surface area, because they are not electrically used. In semiconductor device design, it is often desirable to efficiently utilize the surface area of each material layer, in order to achieve decreased size of the chips and improve performance of the devices, for example.
Thus, what are needed in the art are more efficient ways of utilizing space in semiconductor device material layers.